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PM5366-PI bảng dữ liệu(PDF) 48 Page - PMC-Sierra, Inc |
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PM5366-PI bảng dữ liệu(HTML) 48 Page - PMC-Sierra, Inc |
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48 / 267 page ![]() PRELIMINARY PM5366 TEMAP-84 DATASHEET PMC-2010672 ISSUE 1 HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER PROPRIETARY AND CONFIDENTIAL 36 Pin Name Type Pin No. Function EFBWDAT[3] EFBWDAT[2] EFBWDAT[1] Output F21 B22 A19 The Egress Flexible Bandwidth Data (EFBWDAT[3:1]). These outputs present bit serial data extracted from the System Add Bus (SADATA[7:0]). Only bits for which the associated EFBWEN output is simultaneously high are valid. Each data input is associated with one SPE and is only used when the associated SPE is configured to carry a fractional payload by the OPMODE_SPEx[2:0] bits of the SPE Configuration registers. EFBWDAT[3:1] are updated on the falling edge of the associated EFBWCLK input. EFBWEN[3] EFBWEN[2] EFBWEN[1] Output E22 D20 B18 The Egress Flexible Bandwidth Enables (EFBWEN[3:1]). A logic high on any of these outputs indicates a valid bit on the associated EFBWDAT output. The EFBWEN[3:1] will only be asserted, with a one cycle latency, in response to a sampled logic high on the associated EFBWDREQ, and then only if data is available for presenting on the associated EFBWDAT. EFBWEN[3:1] are updated on the falling edge of the associated EFBWCLK input. Recovered T1 and E1 Clocks RECVCLK1 Output F2 Recovered Clock 1 (RECVCLK1). This clock output is a recovered and de-jittered clock from any one of the 84 1.544 Mbit/s or 63 2.048Mbit/s tributaries. RECVCLK2 Output E4 Recovered Clock 2 (RECVCLK2). This clock output is a recovered and de-jittered clock from any one of the 84 1.544 Mbit/s or 63 2.048Mbit/s tributaries. RECVCLK3 Output G3 Recovered Clock 3 (RECVCLK3). This clock output is a recovered and de-jittered clock from any one of the 84 1.544 Mbit/s or 63 2.048Mbit/s tributaries. |
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