PM5366-PI datasheet(32/267 Pages) PMC

32 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

devised to use a portion of the DS3 payload. Given that these protocols are

subject to change, they are best supported by external programmable logic.

Figure 3 illustrates one implementation. Other implementations and applications

are possible.

In the ingress direction, the framed DS3 is presented to an FPGA, whose

responsibility it is to identify the utilitized bits of the payload. Valid bits are

indicated to the Ingress Flexible Bandwidth Port via an enable signal, IFBWEN.

The bits are collected into bytes by the TEMAP-84 and inserted into the payload

of the SBI Drop bus.

In the egress direction, an FPGA formats the payload of a DS3, while the

TEMAP-84 inserts the DS3 frame overhead. The FPGA contains a data buffer.

Based on the DS3 frame alignment dictated by the TMFPO signal, the FPGA

inserts bits from the data buffer into the DS3 payload according to the protocol

supported. To ensure the data buffer is replenished, the FPGA asserts the

EFBWDREQ signal to initiate the transfer of a bit. The Egress Flexible

Bandwidth Port responds by asserting EFWBEN coincident with EFWBDAT

presenting valid data. The SBI Add bus participates by modulating its

SAJUST_REQ output to match the SBI data rate to that required to keep internal

FIFOs centered.

PM5366-PI bảng dữ liệu(PDF) 32 Page - PMC-Sierra, Inc