PM5366-PI datasheet(241/267 Pages) PMC

tên linh kiện	PM5366-PI

Giải thích chi tiết về linh kiện	HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER

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PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

229

Figure 43: Microprocessor Interface Write Timing

Valid Data

D[7:0]

tVWR

tSAW

tHAW

(CSB+WRB)

A[12:0]

Valid Address

ALE

tVL

tSALW

tSLW

tHALW

tHLW

Notes on Microprocessor Interface Write Timing:

1. A valid write cycle is defined as a logical OR of the CSB and the WRB

signals.

2. In non-multiplexed address/data bus architectures, ALE should be held high

so parameters tSALW, tHALW, tVL, tSLW and tHLW are not applicable.

3. Parameter tHAW is not applicable if address latching is used.

4. When a set-up time is specified between an input and a clock, the set-up

time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4

Volt point of the clock.

5. When a hold time is specified between an input and a clock, the hold time is

the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt

point of the clock.

PM5366-PI bảng dữ liệu(PDF) 241 Page - PMC-Sierra, Inc