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PM5366-PI bảng dữ liệu(PDF) 232 Page - PMC-Sierra, Inc |
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PM5366-PI bảng dữ liệu(HTML) 232 Page - PMC-Sierra, Inc |
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232 / 267 page ![]() PRELIMINARY PM5366 TEMAP-84 DATASHEET PMC-2010672 ISSUE 1 HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER PROPRIETARY AND CONFIDENTIAL 220 Figure 60 - SBI DROP Bus DS3/E3 Functional Timing C1 H3 H3 H3 DS-3 #1 DS-3 #2 DS-3 #3DS-3 #1 SREFCLK SC1FP SDDATA[7:0 ] SDPL SDV5 SDDP ••• ••• ••• ••• ••• ••• Figure 60 shows three DS-3 tributaries mapped onto the SBI bus. A negative justification is shown for DS-3 #2 during the H3 octet with SDPL asserted high. A positive justification is shown for DS-3#1 during the first DS-3#1 octet after H3 which has SDPL asserted low. E3 is transported by the same mechanism. 13.7 SBI ADD Bus Interface Timing The SBI ADD bus functional timing for the transfer of tributaries whether T1/E1 or DS3 is the same as for the SBI DROP bus. The only difference is that the SBI ADD bus has one additional signal: the SAJUST_REQ output. The SAJUST_REQ signal is used to by the TEMAP-84 in SBI master timing mode to provide transmit timing to SBI link layer devices. Figure 61 - SBI ADD Bus Justification Request Functional Timing C1 H3 H3 H3 DS-3 #1 DS-3 #2 DS-3 #3DS-3 #1 SREFCLK SC1FP SADATA[7:0] SAPL SAV5 SADP SAJUST_REQ ••• ••• ••• ••• ••• ••• ••• |
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