CS44800 datasheet(23/80 Pages) CIRRUS

23 / 80 page

DS632F1

CS44800

4. APPLICATIONS

4.1

Overview

The CS44800 is a multi-channel digital-to-PWM Class D audio system controller including interpolation,

sample rate conversion, half- and full-bridge PWM driver outputs, and power supply rejection feedback in a

64-pin LQFP package. The architecture uses a direct-to-digital approach that maintains digital signal integ-

rity to the final output filter, minimizing analog interference effects which negatively affect system perfor-

mance.

The CS44800 integrates on-chip sample rate conversion, digital volume control, peak detect with volume

limiter, de-emphasis, programmable interrupt conditions, and the ability to change the PWM switch rate to

eliminate AM frequency interference. The CS44800 also has a programmable load compensation filter,

which allows the speaker load to vary while the output filter remains fixed, maintaining a flat frequency re-

sponse. For single-ended half-bridge applications PWM Popguard® reduces the transient pops and clicks

and realtime power supply feedback reduces noise coupling from the power supply. The PWM amplifier can

achieve greater than 90% efficiency. This efficiency provides for a smaller device package, less heat sink

requirements, and smaller power supplies.

The CS44800 is ideal for audio systems requiring wide dynamic range, negligible distortion, and low noise

such as A/V receivers, DVD receivers, digital speaker, and automotive audio systems.

4.2

Feature Set Summary

Core Features

•

2.5 V digital core voltage, VD.

•

VLC voltage pin for host interface logic levels between 2.5 V and 5.0 V.

•

VLS voltage pin for digital audio interface logic levels between 2.5 V and 5.0 V.

•

VDP voltage pin for PWM backend interface logic levels between 3.3 V and 5.0 V.

•

VDX voltage pin for clock input signals between 2.5 V and 5.0 V.

Clocking

•

Minimum of 128Fs DAI_MCLK for DAI serial interface.

•

DAI interface uses automatic detection of LRCK/MCLK ratio to configure internal DAI/SRC clocks.

•

All PWM Processing clocks generated internally via:

–

An external crystal - 24.576 MHz to 54 MHz, or

–

XTI input pin capable of supporting a clock signal at the VDX voltage level.

•

Programmable divide of XTI by 1, 2, 4, 8 for SYS_CLK output.

•

Programmable divide of XTI by 32, 64, 128, 256 for PS_SYNC (power supply synchronization signal).

Digital Audio Playback

•

Supports 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz and 192 kHz sample frequencies.

•

High performance sample rate converter.

•

16, 20 and 24 bit audio sample lengths.

•

De-emphasis for 32 kHz, 44.1 kHz, 48 kHz.

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