CS44800 datasheet(69/80 Pages) CIRRUS

69 / 80 page

DS632F1

CS44800

er-down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)”

on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.

7.29.4

Channel A3 Output Configuration (A3_OUT_CNFG)

Default = 0

0 - pwm outputs for channel A3 are configured for half-bridge operation

1 - pwm outputs for channel A3 are configured for full-bridge operation

Function:

Identifies the output configuration. The value selected for this bit is applicable to the outputs for only chan-

nel A3. This parameter can only be changed when all modulators and associated logic are in the power

down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)”

on page 51 to a ‘1’b. Attempts to write this register while the PDN is not set will be ignored.

7.29.5

Channel B3 Output Configuration (B3_OUT_CNFG)

Default = 0

0 - pwm outputs for channel B3 are configured for half-bridge operation

1 - pwm outputs for channel B3 are configured for full-bridge operation

Function:

Identifies the output configuration. The value selected for this bit is applicable to the outputs for only chan-

nel B3. This parameter can only be changed when all modulators and associated logic are in the power-

down state by setting the PDN bit in the register “Clock Configuration and Power Control (address 02h)”

on page 51 to a 1b. Attempts to write this register while the PDN is not set will be ignored.

7.29.6

Channels A4 and B4 Output Configuration (A4/B4_OUT_CNFG)

Default = 0

0 - pwm outputs for both channels A4 and B4 are configured for half-bridge operation

1 - pwm outputs for both channels A4 and B4 are configured for full-bridge operation

Function:

Identifies the output configuration. The value selected for this bit is applicable to the outputs for chan-

nels A4 and B4. This parameter can only be changed when all modulators and associated logic are

in the power down state by setting the PDN bit in the register “Clock Configuration and Power Control

(address 02h)” on page 51 to a ‘1’b. Attempts to write this register while the PDN is not set will be

ignored.

7.30

PWM Minimum Pulse Width Register (address 32h)

7.30.1

Disable PWMOUTXX - Signal (DISABLE_PWMOUTXX-)

Default = 0

0 - PWM minus (“-”) differential signal is operational when PWM channel is configured for half-bridge.

1 - PWM minus (“-”) differential signal is disabled when PWM channel is configured for half-bridge.

Function:

Determines if the PWM minus (“-”) differential signal is disabled when the particular PWM channel is con-

figured for half-bridge operation. This bit is ignored for channels configured for full-bridge operation. The

value selected for this bit is applicable to the outputs for all channels configured for half-bridge operation.

This parameter can only be changed when all modulators and associated logic are in the power-down

DISABLE_PWMOUTXX- RESERVED

RESERVED MIN_PULSE4 MIN_PULSE3

MIN_PULSE2

MIN_PULSE1

MIN_PULSE0

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