WM8804 datasheet(25/66 Pages) WOLFSON

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Production Data

WM8804

PD Rev 4.1 September 2007

OSC

CLK

(MHz)

PRE-

SCALE

(MHz)

PLL_N

(Hex)

PLL_K

(Hex)

FREQ

MODE

[1:0]

MCLK

DIV

MCLK

(MHz)

CLKOUT

DIV

[1:0]

CLK

OUT

(MHz)

98.304

8.192

C49BA

24.576

49.152

98.304

8.192

C49BA

12.288

24.576

98.304

8.192

C49BA

6.144

12.288

98.304

8.192

C49BA

12.288

6.144

98.304

8.192

C49BA

6.144

3.072

90.3168

7.5264

21B089

22.5792

45.1584

90.3168

7.5264

21B089

11.2896

22.5792

90.3168

7.5264

21B089

5.6448

11.2896

90.3168

7.5264

21B089

11.2896

5.6448

90.3168

7.5264

21B089

5.6448

2.8224

13.5

98.304

7.2818

1208A5

12.288

13.5

98.304

7.2818

1208A5

6.144

13.5

90.3168

6.6901

2C2B24

11.2896

13.5

90.3168

6.6901

2C2B24

5.6448

Table 23 User Mode PLL Configuration Examples

When considering settings not shown in this table, the key configuration parameters which must be

selected for optimum operation are:

•

90MHz

≤ f2 ≤ 100MHz

•

≤ PLL_N ≤ 13

•

OSCCLOCK = 10 to 14.4MHz or 16.28 to 27MHz

PLL INTEGER AND FRACTIONAL CONTROL MODES

The PLL can be operated in either fractional or integer control modes. In PLL User Mode, it is

recommended that the PLL should be operated in fractional control mode at all times. When

the S/PDIF receiver is enabled, the PLL must be operated in fractional control mode.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

PLL5

07h

FRACEN

Integer/Fractional PLL Mode

Select

0 = Integer PLL (PLL_N value used,

PLL_K value ignored)

1 = Fractional PLL (both PLL_N and

PLL_K values used)

Note: FRACEN must be set to

enable the fractional PLL when

using S/PDIF Receive Mode.

Table 24 PLL Fractional/Integer Mode Select

MASTER CLOCK (MCLK)

The master clock (MCLK) signal is used to supply reference clock signals to the following circuit

blocks:

•

The Digital Audio Interface

•

The S/PDIF Transmitter

The master clock (MCLK) pin can be configured as either a clock input or output depending on the

digital audio interface mode as shown in Table 25.

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