WM8804 datasheet(61/66 Pages) WOLFSON

61 / 66 page

Production Data

WM8804

PD Rev 4.1 September 2007

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

AIFRX_LRP

Right, left and I2S modes – LRCLK polarity and

DSP mode select

1 = invert LRCLK polarity / DSP Mode B

0 = normal LRCLK polarity / DSP Mode A

AIF_MS

Audio Interface Master/Slave Interface

Select

0 = Slave Mode – LRCLK, BCLK are inputs

1= Master Mode – LRCLK and BCLK are

outputs

2:0

READMUX

[2:0]

000

Status Register Select

Determines which status register is to be read

back:

000 = Interrupt Status Register

001 = Channel Status Register 1

010 = Channel Status Register 2

011 = Channel Status Register 3

100 = Channel Status Register 4

101 = Channel Status Register 5

110 = S/PDIF Status Register

CONT

Continuous Read Enable

0 = Continuous read-back mode disabled

1 = Continuous read-back mode enabled

WITHFLAG

‘With Flags’ Mode Select

0: ‘With Flags’ Mode disabled

1: ‘With Flags’ Mode enabled

WL_MASK

S/PDIF Receiver Word Length Truncation

Mask

0 = disabled, data word is truncated as

described in Table 44 S/PDIF Receiver

Channel Status Register 5

1 = enabled, data word is not truncated.

R29

SPDRX1

1Dh

SPD_192K_EN

S/PDIF Receiver 192kHz Support Enable

0 = disabled, S/PDIF receiver maximum

supported sampling frequency is 96kHz

1 = enabled, S/PDIF receiver maximum

supported sampling frequency is 192kHz

WM8804 bảng dữ liệu(PDF) 61 Page - Wolfson Microelectronics plc

WM8804 bảng dữ liệu(HTML) 61 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

bảng dữ liệu tải về

Link URL