TAS2120 datasheet(22/63 Pages) TI

22 / 63 page

When the signal level increases above the VDD_MODE_THR_LVL[23:0] plus VDD_MODE_HYST[23:0], the

device starts switching the output PWM signal on PVDD supply without introducing any signal clipping.

The VDD_MODE_THR_LVL[23:0] and VDD_MODE_HYST[23:0] registers can be configured using the PPC3

Software Section 6.4.1.

Table 6-10. VDD Y-bridge hysteresis timer

YBRIDGE_HYST_TIMER[1:0]

Configuration

100us

01 (default)

500us

5ms

50ms

Table 6-11. VDD Y-bridge enable

EN_Y_BRIDGE_MODE

Configuration

Y-bridge mode is disabled

1 (default)

Y-bridge mode is enabled

6.3.1.4.4 Class-H Boost

TAS2120 has an advanced class-H algorithm to control the integrated Boost. The class-H algorithm enables

Boost supply to closely track audio signal levels and achieve high system level efficiency for extending battery

life. Class-H mode is enabled using the BST_MODE[1:0] register.

The class-H algorithm buffers the input signal to enable sufficient look-ahead time required to charge the Boost

output capacitor and avoid any signal clipping. The algorithm monitors the input signal level and uses system-

level parameters configured in PPC3 software like Boost output voltage, Boost output capacitor, channel gain,

and so forth. and computes the most optimum class-H tuning parameters. These tuning parameter registers are

then calculated in the PPC3 software and configured in the corresponding CLASSH_TUNING_x[23:0] registers.

When the BST_MODE[1:0] is configured to use the device in Class-G mode or Boost always-ON mode, the max

inrush current from the battery can be controlled by setting the Inrush current parameter in PPC3 software. The

software generates the required coefficients in the CLASSH_TUNING_x[23:0] register based on the system level

parameters configured like Boost output capacitor, Inrush current required, and so forth.

6.3.1.5 2S Battery Mode

TAS2120 can be configured to function for different battery systems like single series cell (1S) Li-ion battery (2.5

V to 5.5 V) or 2-series cell (2S) series cell battery (4.7 V to 10 V). When the 2S battery is selected for the device,

the diagram below shows the conceptual connections in the system to connect the 2S battery. When selected

for 2S battery operation, the VBAT pin of the device is used for biasing internal blocks and needs to be supplied

from external power source between 3.0 V to 5.5 V.

The internal battery voltage monitor needs to be switched to sense the voltage on the VBAT_SNS pin instead of

the default sensing done on the VBAT pin. SEL_VBAT_MODE[1:0] configures the internal voltage monitor and

the device configuration between 1S or 2S battery systems.

When SEL_VBAT_MODE[1:0] is set as '10', ie 2S mode of operation, the device internal bias voltage needs

to be configured based on VBAT_BIAS_SELx registers. If the VBAT pin voltage is available from the center

tap or half of the 2S battery voltage, the VBAT_BIAS_SEL1 needs to be set high. For other VBAT voltage

configurations the VBAT_BIAS_SEL1 should be set low and appropriate VBAT_BIAS_SEL2 configuration should

be selected.

TAS2120

SLASFC6 – AUGUST 2024

www.ti.com

Submit Document Feedback

Product Folder Links: TAS2120

TAS2120 bảng dữ liệu(PDF) 22 Page - Texas Instruments

TAS2120 bảng dữ liệu(HTML) 22 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

bảng dữ liệu tải về

Link URL