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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TAS2120 bảng dữ liệu(PDF) 13 Page - Texas Instruments |
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TAS2120 bảng dữ liệu(HTML) 13 Page - Texas Instruments |
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13 / 63 page  5.5 Electrical Characteristics (continued) TA = 25 °C, VBAT = 3.6 V, VBAT2S = 7.2V (2S mode enabled), PVDD = 12 V ( External PVDD mode enabled), VDD = 1.8 V, IOVDD = 1.8V RL = 8Ω + 33µH, LBOOST = 1µH, fin = 1 kHz, fs = 48 kHz, Gain = 21dBV, BST_ILIM (1S battery) = 5.1A, BST_ILIM (2S battery, HW mode)=4.1A, BST_ILIM (2S battery, I2C mode)=5.1A, SDZ = 1, Noise gate disabled, Measured filter free with an Audio Precision using 22 Hz to 20 kHz un-weighted bandwidth (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOL(IRQZ) Low-level digital output voltage for open drain output IRQZ pin; IOL = -1mA 0.2 V IIH Input logic-high leakage for digital inputs All digital pins; Input = IOVDD. -1 1 µA IIL Input logic-low leakage for digital inputs All digital pins; Input = GND -1 1 µA CIN Input capacitance for digital inputs All digital pins 5 pF RPD Pull down resistance for digital input/IO pins when asserted on All digital pins. Pull down resistance option enabled 18 kΩ 5.6 Timing Requirements TA = 25 °C, VDD = IOVDD = 1.8 V (unless other wise noted) MIN NOM MAX UNIT I2C - Standard-Mode fSCL SCL clock frequency 0 100 kHz tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 μs tLOW LOW period of the SCL clock 4.7 μs tHIGH HIGH period of the SCL clock 4 μs tSU;STA Setup time for a repeated START condition 4.7 μs tHD;DAT Data hold time: For I2C bus devices 0 3.45 μs tSU;DAT Data set-up time 250 ns tr SDA and SCL rise time 1000 ns tf SDA and SCL fall time 300 ns tSU;STO Set-up time for STOP condition 4 μs tBUF Bus free time between a STOP and START condition 4.7 μs Cb Capacitive load for each bus line 400 pF I2C - Fast-Mode fSCL SCL clock frequency 0 400 kHz tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 0.6 μs tLOW LOW period of the SCL clock 1.3 μs tHIGH HIGH period of the SCL clock 0.6 μs tSU;STA Setup time for a repeated START condition 0.6 μs tHD;DAT Data hold time: For I2C bus devices 0 0.9 μs tSU;DAT Data set-up time 100 ns tr SDA and SCL rise time 20 + 0.1 × Cb 300 ns tf SDA and SCL fall time 20 + 0.1 × Cb 300 ns tSU;STO Set-up time for STOP condition 0.6 μs tBUF Bus free time between a STOP and START condition 1.3 μs Cb Capacitive load for each bus line 400 pF I2C - Fast-Mode Plus TDM Port www.ti.com TAS2120 SLASFC6 – AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TAS2120 |
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