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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TAS2120 bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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TAS2120 bảng dữ liệu(HTML) 8 Page - Texas Instruments |
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8 / 63 page  5.5 Electrical Characteristics (continued) TA = 25 °C, VBAT = 3.6 V, VBAT2S = 7.2V (2S mode enabled), PVDD = 12 V ( External PVDD mode enabled), VDD = 1.8 V, IOVDD = 1.8V RL = 8Ω + 33µH, LBOOST = 1µH, fin = 1 kHz, fs = 48 kHz, Gain = 21dBV, BST_ILIM (1S battery) = 5.1A, BST_ILIM (2S battery, HW mode)=4.1A, BST_ILIM (2S battery, I2C mode)=5.1A, SDZ = 1, Noise gate disabled, Measured filter free with an Audio Precision using 22 Hz to 20 kHz un-weighted bandwidth (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POUT_EXT _PVDD Maximum Continuous Output Power - 1% THDN RL = 8 Ω + 33 µH, HW pin control mode 8.3 W POUT_EXT _PVDD Maximum Continuous Output Power - 10% THDN RL = 8 Ω + 33 µH 10.3 W RL = 4 Ω + 33 µH 18.4 W RL = 4 Ω + 33 µH, PVDD=14V 24.5 W ηSYSTEM_ EXT_0.5W System Efficiency at POUT = 0.5W RL = 8 Ω + 33 µH 83.9 % RL = 4 Ω + 33 µH 80.0 % ηSYSTEM_ _EXT_1W System Efficiency at POUT = 1.0W RL = 8 Ω + 33 µH 88.1 % RL = 4 Ω + 33 µH 84.2 % ηSYSTEM_ _EXT_1W System Efficiency at POUT = 1.0W RL = 8 Ω + 33 µH, HW pin control mode 88.1 % ηSYSTEM_ EXT_MAX_ POUT System Efficiency at 1% THD+N power Level RL = 8 Ω + 33 µH 93.2 % RL = 4 Ω + 33 µH 88.5 % ηSYSTEM_ EXT_MAX_ POUT System Efficiency at 1% THD+N power Level RL = 8 Ω + 33 µH, HW pin control mode 93.2 % VN_EXT Idle channel Noise A-Weighted, Gain = 21dBV (Speaker Mode), DAC-Running 14.4 µV DNR_EX T Dynamic Range A-Weighted, -60 dBFS Method, RL = 8 Ω + 33 µH 114.4 dB THD+N_ EXT Total Harmonic distortion + Noise POUT = 1 W, RL = 8 Ω + 33 µH, fin = 1 kHz 0.003 % POUT = 1 W, RL = 4 Ω + 33 µH, fin = 1 kHz 0.004 % KCP_EXT Click and pop performance All dynamic power up/downs of audio channel except for faults. Includes In/Out of Mute, Power Up and power Down, Noise Gate mode entry and Exit. Measured at Peak A-weighted Voltage. RL = 8 Ω + 33 µH, Input = Digital Silience –68 dBV VOS_EX T Output Offset Voltage Idle channel –1 1 mV PSRRPV DD_EXT PVDD power-supply rejection ratio PVDD = 12 V + 200 mVpp, fripple = 217 Hz 115 dB PVDD = 12 V + 200 mVpp, fripple = 1 kHz 115 dB PVDD = 12 V + 200 mVpp, fripple = 20 kHz 95 dB PSRRVB AT_EXT VBAT power-supply rejection ratio VBAT = 3.6 V + 200 mVpp, fripple = 217 Hz 115 dB VBAT = 3.6 V + 200 mVpp, fripple = 1 kHz 115 dB VBAT = 3.6 V + 200 mVpp, fripple = 20 kHz 90 dB PSRRVD D_EXT VDD power-supply rejection ratio VDD = 1.8 V + 200 mVpp, fripple = 217 Hz 110 dB VDD = 1.8 V + 200 mVpp, fripple = 1 kHz 110 dB VDD = 1.8 V + 200 mVpp, fripple = 20 kHz 90 dB Boost Converter VBOOST_ RANGE Max Output Voltage programmability Range Programmable in steps of 66mV 5.5 14.75 V VBOOST_S TEP Class-H Output Voltage Step Size 33 mV TAS2120 SLASFC6 – AUGUST 2024 www.ti.com 8 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TAS2120 |
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