M24M02E-F datasheet(4/54 Pages) STMICROELECTRONICS

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Signal description

2.1

Serial clock (SCL)

SCL is an input. The signal applied on it is used to strobe the data available on SDA(in) and to output the data on

SDA(out).

2.2

Serial data (SDA)

SDA is an input/output used to transfer data in or out of the device. SDA(out) is an open drain output that can be

wired

‑AND with other open drain or open collector signals on the bus. A pull‑up resistor must be connected from

serial data (SDA) to VCC (Figure 25 and Figure 26 indicate how to calculate the value of the pull

‑up resistor).

2.3

Write control (WC)

This input signal is useful for protecting the contents of the memory, registers, and identification page from

inadvertent write operations. All write operations are disabled when the WC is driven high. All write operations are

enabled when the WC is either driven low or left floating.

When it is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged.

2.4

VSS (ground)

VSS is the reference for the VCC supply voltage.

2.5

Supply voltage (VCC)

2.5.1

Operating supply voltage (VCC)

Before selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified

[VCC(min), VCC(max)] range must be applied (see operating conditions in Section 9: DC and AC parameters). To

secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually

from 10 nF to 100 nF) close to the VCC/VSS package pins.

This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write

instruction, until the completion of the internal write cycle (tW).

2.5.2

Power-up conditions

The VCC voltage must rise continuously from 0 V up to the minimum VCC operating voltage (see operating

conditions in Section 9: DC and AC parameters).

Once the VCC is greater than or equal to the minimum VCC level, the controller must wait for at least tWU before

sending the first command to the device. See Table 19 and Table 20 for the value of the wake-up time parameter.

2.5.3

Device reset

To prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included.

At power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold

voltage. This threshold is lower than the minimum VCC operating voltage (see operating conditions in

Section 9: DC and AC parameters). When VCC passes over the POR threshold, the device is reset and enters the

standby power mode; the device must not be accessed until VCC reaches a valid and stable DC voltage within the

specified [VCC(min), VCC(max)] range (see operating conditions in Section 9: DC and AC parameters).

Similarly, during power-down, when the VCCdecrease, the device must not be accessed once VCC drops below

VCC(min). When VCC drops below the power-on-reset threshold voltage, the device stops responding to any

instruction sent to it.

2.5.4

Power-down conditions

During power-down, when the VCC decreases, the device must be in the standby power mode (the mode is

reached after decoding a stop condition, with no internal write cycle in progress).

M24M02E-F

Signal description

DS14157 - Rev 2

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