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M24M02E-F bảng dữ liệu(PDF) 12 Page - STMicroelectronics

tên linh kiện M24M02E-F
Giải thích chi tiết về linh kiện  2-Mbit serial I²C bus EEPROM with configurable device address, software write protection registers, and preprogrammed device address
PDF  54 Pages
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5.5
Device addressing
To start communication between the bus controller and the target device, the bus controller must initiate a start
condition. Following this and unless the product is delivered with the pre-programmed device address, the bus
controller sends the device select code and byte address as specified in Table 9, Table 10, and Table 11. When
the device select code is received, the device responds only if the bit b3 value matches the value of the C2 bit
programmed in the configurable device address register.
If a match occurs, the corresponding device gives an acknowledgment on serial data (SDA) during the ninth bit
time. If the device does not acknowledge the device select code, the device deselects itself from the bus, and
goes into standby mode (therefore it does not acknowledge the device select code).
The eighth bit is the read/write bit (RW). This bit is set to 1 for read and 0 for write operations.The 256
‑Kbyte
(2
‑Mbit) are addressed with 18 address bits, the 16 lower address bits being defined by the two address bytes
and the most significant address bit (A17 and A16) being included in the device select code (see Table 9).
Table 9. Device select code
Features
Device type identifier bits
Chip enable address bits(1) Address bit
RW
Bit 7 (MSB)(2) Bit 6 Bit 5 Bit 4
Bit 3
Bit 2 Bit 1 Bit 0 (LSB)
Memory
1
0
1
0
C2
A17
A16
RW
Device type identifier
1
0
1
1
C2
X
X(3)
RW
Configurable device address
1
0
1
1
C2
X
X
RW
Software write protection
1
0
1
1
C2
X
X
RW
Identification page
1
0
1
1
C2
X
X
RW
Identification page lock
1
0
1
1
C2
X
X
RW
1. C2 is compared with the value read on bit b3 of the CDA register.
2. The most significant bit, b7, is sent first.
3. X = Don't care bit
Table 10. First byte address
Features
Bit 7 (MSB)(1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Memory
A15
A14
A13
A12
A11
A10
A9
A8
Device type identifier
1
1
1
X(2)
X
X
X
X
Configurable device address
1
1
0
X
X
X
X
X
Software write protection
1
0
1
X
X
X
X
X
Identification page
0
0
0
X
X
X
X
X
Identification page lock
0
1
1
X
X
X
X
X
1. The most significant bit, b7, is sent first.
2. X = Don't care bit.
M24M02E-F
Device operation
DS14157 - Rev 2
page 12/54



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