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M24M02E-F bảng dữ liệu(PDF) 17 Page - STMicroelectronics |
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M24M02E-F bảng dữ liệu(HTML) 17 Page - STMicroelectronics |
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17 / 54 page ![]() 6.2 Write operations on features 6.2.1 Write operation on DTI register Write operations on the device type identifier (DTI) register are not allowed. The register is delivered locked in read-only. 6.2.2 Write operation on CDA register Write operations on the configurable device address register are performed according to the state of the device address lock bit (DAL) or the status of the WC line. If the configurable device address register is write protected by software with DAL = 1 or hard protected with WC line driven high, the write operation on this register is not executed and the accompanying data byte is not acknowledged as shown in Figure 9. Following a start condition the bus controller sends a device select code with the R/W bit (RW) set to 0. The device acknowledges this, as shown in Figure 8, and waits for the address bytes where the register is located. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. See in Table 9, Table 10, and Table 11 how to address the configurable device address register. When the bus controller generates a stop condition immediately after the data byte ACK bit (in the tenth bit time slot), the internal write cycle tW is triggered. A stop condition at any other time slot does not trigger the internal write cycle. During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any requests (NO ACK). If the bit C2 has been reconfigured with a correct write command, the device acknowledges if the chip enable address of the device select code is equal to the new value of C2, otherwise no ACK. Sending more than one byte aborts the write cycle (configurable device address content does not change). Bits (C2, DAL) can be updated (DAL = 0 to 1) in the same program instruction. Figure 8. Write CDA register (data write enabled) Dev sel Byte addr Byte addr Data in ACK RW ACK ACK ACK Figure 9. Write CDA register (data write inhibited) Byte addr Data in ACK ACK ACK NO ACK R/W Byte addr Dev sel M24M02E-F Instructions DS14157 - Rev 2 page 17/54 |
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