PIC18F44J10-ESLASHSP datasheet(90/358 Pages) MICROCHIP

90 / 358 page

PIC18F45J10 FAMILY

DS39682C-page 88

Preliminary

8.4

IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are three Peripheral

Interrupt Priority registers (IPR1, IPR2, IPR3). Using

the priority bits requires that the Interrupt Priority

Enable (IPEN) bit be set.

IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1

R/W-1

PSPIP(1)

ADIP

RCIP

TXIP

SSP1IP

CCP1IP

TMR2IP

TMR1IP

bit 7

bit 0

bit 7

PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)

=High priority

= Low priority

Note:

This bit is not implemented on 28-pin devices and should be read as ‘0’.

bit 6

ADIP: A/D Converter Interrupt Priority bit

=High priority

= Low priority

bit 5

RCIP: EUSART Receive Interrupt Priority bit

=High priority

= Low priority

bit 4

TXIP: EUSART Transmit Interrupt Priority bit

=High priority

= Low priority

bit 3

SSP1IP: Master Synchronous Serial Port 1 Interrupt Priority bit

=High priority

= Low priority

bit 2

CCP1IP: ECCP1/CCP1 Interrupt Priority bit

=High priority

= Low priority

bit 1

TMR2IP: TMR2 to PR2 Match Interrupt Priority bit

=High priority

= Low priority

bit 0

TMR1IP: TMR1 Overflow Interrupt Priority bit

=High priority

= Low priority

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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