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M68HC08 bảng dữ liệu(PDF) 91 Page - Freescale Semiconductor, Inc

tên linh kiện M68HC08
Giải thích chi tiết về linh kiện  Microcontrollers
PDF  288 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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M68HC08 bảng dữ liệu(HTML) 91 Page - Freescale Semiconductor, Inc

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System Integration Module (SIM)
MC68HC908BD48 — Rev. 2.1
Data Sheet
Freescale Semiconductor
System Integration Module (SIM)
91
7.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, OSCOUT, as shown in Figure 7-2.
Figure 7-2. OSC Clock Signals
7.3.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency
(OSCXCLK) divided by four.
7.3.2 Clock Start-Up from POR
When the power-on reset module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after
the 4096 OSCXCLK cycle POR timeout has completed. The RST is
driven low by the SIM during this entire period. The IBUS clocks start
upon completion of the timeout.
7.3.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode (by an interrupt, break, or reset), the SIM
allows OSCXCLK to clock the SIM counter. The CPU and peripheral
clocks do not become active until after the stop delay timeout. This
timeout is selectable as 4096 or 32 OSCXCLK cycles. (See 7.7.2 Stop
Mode.)
SIMOSCEN
OSCXCLK
From
SIM
÷ 2
OSCOUT
OSC1
OSC2
÷ 2
BUS CLOCK
GENERATORS
SIM
SIM COUNTER
OSCILLATOR



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