NAND512R3A2C datasheet(31/51 Pages) STMICROELECTRONICS

31 / 51 page

NAND512-A2C

Software algorithms

31/51

An ECC model is available in VHDL or Verilog. Contact the nearest ST Microelectronics

sales office for more details.

Figure 15.

Error Detection

7.6

Hardware simulation models

7.6.1

Behavioral simulation models

Denali Software Corporation models are platform independent functional models designed

to assist customers in performing entire system simulations (typical VHDL/Verilog). These

models describe the logic behavior and timings of NAND Flash devices, and so allow

software to be developed before hardware.

7.6.2

IBIS simulations models

IBIS (I/O Buffer Information Specification) models describe the behavior of the I/O buffers

and electrical characteristics of Flash devices.

These models provide information such as AC characteristics, rise/fall times and package

mechanical data, all of which are measured or simulated at voltage and temperature ranges

wider than those allowed by target specifications.

IBIS models are used to simulate PCB connections and can be used to resolve compatibility

issues when upgrading devices. They can be imported into SPICETOOLS.

New ECC generated

during read

XOR previous ECC

with new ECC

All results

= zero?

22 bit data = 0

YES

11 bit data = 1

1 bit data = 1

Correctable

Error

ECC Error

No Error

ai08332

>1 bit

= zero?

YES

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