NAND512R3A2C datasheet(25/51 Pages) STMICROELECTRONICS

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NAND512-A2C

Device operations

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6.5

Block Erase

Erase operations are done one block at a time. An erase operation sets all of the bits in the

addressed block to ‘1’. All previous data in the block is lost.

An erase operation consists of three steps (refer to Figure 12):

One bus cycle is required to setup the Block Erase command.

Only three bus cycles for 512Mb and 1Gb devices, or two for 128Mb and 256Mb

devices are required to input the block address. The first cycle (A0 to A7) is not

required as only addresses A14 to A25 are valid, A9 to A13 are ignored. In the last

address cycle I/O2 to I/O7 must be set to VIL.

One bus cycle is required to issue the confirm command to start the P/E/R Controller.

Once the erase operation has completed the Status Register can be checked for errors.

Figure 12.

Block Erase operation

6.6

Reset

The Reset command is used to reset the Command Interface and Status Register. If the

Reset command is issued during any operation, the operation will be aborted. If it was a

program or erase operation that was aborted, the contents of the memory locations being

modified will no longer be valid as the data will be partially programmed or erased.

If the device has already been reset then the new Reset command will not be accepted.

The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value

of tBLBH4 depends on the operation that the device was performing when the command was

issued, refer to Table 21 for the values.

I/O

Block Address

Inputs

SR0

ai07593

D0h

70h

60h

Block Erase

Setup Code

Confirm

Code

Read Status Register

Busy

tBLBH3

(Erase Busy time)

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