NAND512R3A2C datasheet(18/51 Pages) STMICROELECTRONICS

tên linh kiện	NAND512R3A2C

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Command set

NAND512-A2C

18/51

Command set

All bus write operations to the device are interpreted by the Command Interface. The

Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when

the Command Latch Enable signal is high. Device operations are selected by writing

specific commands to the Command Register. The two-step command sequences for

program and erase operations are imposed to maximize data security.

The Commands are summarized in Table 9.

Table 9.

Commands

Command

Bus Write operations(1)(2)

The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or

input/output data are not shown.

Any undefined command sequence will be ignored by the device.

Command

accepted during

busy

1st CYCLE

2nd CYCLE

3rd CYCLE

Read A

00h

Read B(3)

The Read B command (code 01h) is not used in x16 devices.

01h

Read C

50h

Read Electronic Signature

90h

Read Status Register

70h

Yes

Page Program

80h

10h

Copy Back Program

00h

8Ah

(10h)(4)

The Program Confirm command (code 10h) is no more necessary for NAND512-A2C devices. It is optional

and has been maintained for backward compatibility

Block Erase

60h

D0h

Reset

FFh

Yes

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