PI6C484321 datasheet(2/9 Pages) PERICOM

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PS8765A

08/01/05

PI6C484321

260MHz Crystal-to-3.3V Differential

LVPECL Frequency Synthesizer

Functional Description

The following functional description describes operations using

a 25MHz crystal. Valid PLL loop divider values for different

crystal or input frequencies are defined in the Input Frequency

Characteristics, Table 5, NOTE 1.

The PI6C484321 features a fully integrated PLL, thus requires

no external components for setting the loop bandwidth. A funda-

mental crystal is the input to the internal oscillator. The output

of the oscillator is fed into the phase detector. A 25MHz crystal

provides a 25MHz reference frequency to the phase detector. The

actual VCO range of the PLL is 320MHz to 1.1GHz. The output

of the M divider is used by the phase detector.

The phase detector and the M divider force the VCO output

frequency to be M times the reference frequency by adjusting

the VCO control voltage. Note that for some illegal values of M

(either too high or too low), the PLL will not achieve lock. The

output of the VCO is scaled by a divider prior to being sent to

each of the LVPECL output buffers. The divider provides a 50%

output duty cycle.

The programmable feature that selects the M divider and N out-

put divider supports two modes: parallel and serial modes. Figure

1 shows the timing diagram for each mode. In parallel mode, the

nP_LOAD input is initially LOW. The data on inputs M0 through

M8 and N0 and N1 is passed directly to the M divider and N out-

put divider. On the LOW-to-HIGH transition of the nP_LOAD

input, the data is latched and the M divider remains loaded until

the next LOW transition on nP_LOAD or until a serial event oc-

curs. As a result, the M and N bits can be hardwired to set the

M divider and N output divider to a specific default state that

will automatically occur during power-up. The TEST output is

LOW when operating in the parallel input mode. The relation-

ship between the VCO frequency, the crystal frequency and the

TEST Output

LOW

S_Data

Output of M divider

CMOS Fout

Parallel & Serial Load Operations

M divider is defined as follows:

fVCO = fxtal x M

The M value and the required values of M0 through M8 are

shown in Table 3B to program the VCO Frequency Function

Table. The output frequency is defined as follows:

Serial operation occurs when nP_LOAD is HIGH and S_LOAD

is LOW. The shift register is loaded by sampling the S_DATA

bits with the rising edge of S_CLOCK. The contents of the shift

S_LOAD transitions from LOW-to-HIGH. The M divide and N

output divide values are latched on the HIGH-to-LOW transition

of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA in-

put is passed directly to the M divider and N output divider on

each rising edge of S_CLOCK. The serial mode can be used to

program the M and N bits and test bits T1 and T0. The internal

registers T0 and T1 determine the state of the TEST output as

follows:

fOUT = fVCO = fxtal x M

Time

SERIAL LOADING

PARALLEL LOADING

M, N

T 1

*NULL

M 0

S_CLOCK

S_DATA

S_LOAD

nP_LOAD

M0:M8, N0:N1

nP_LOAD

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