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XRT86VL34 bảng dữ liệu(PDF) 94 Page - Exar Corporation |
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XRT86VL34 bảng dữ liệu(HTML) 94 Page - Exar Corporation |
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94 / 156 page ![]() XRT86VL34 89 QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0 2 SLIP RO 0 Slip Buffer Block Interrupt Status This bit indicates whether or not the Slip Buffer block has any out- standing interrupt request awaiting service. 0 = Indicates no outstanding Slip Buffer Block interrupt request is awaiting service 1 = Indicates Slip Buffer block has an interrupt request awaiting ser- vice. Interrupt Service routine should branch to the interrupt source and read the Slip Buffer Interrupt Status register (address 0xnB08) to clear the interrupt NOTE: This bit will be reset to 0 after the microprocessor has performed a read to the Slip Buffer Interrupt Status Register. 1 ALARM RO 0 Alarm & Error Block Interrupt Status This bit indicates whether or not the Alarm & Error Block has any outstanding interrupt request awaiting service. 0 = Indicates no outstanding interrupt request is awaiting service 1 = Indicates the Alarm & Error Block has an interrupt request await- ing service. Interrupt service routine should branch to the interrupt source and read the corresponding alarm and error status registers (address 0xnB02, 0xnB0E, 0xnB40) to clear the interrupt. NOTE: This bit will be reset to 0 after the microprocessor has performed a read to the corresponding Alarm & Error Interrupt Status register that generated the interrupt. 0 T1 FRAME RO 0 T1 Framer Block Interrupt Status This bit indicates whether or not the T1 Framer block has any out- standing interrupt request awaiting service. 0 = Indicates no outstanding interrupt request is awaiting service. 1 = Indicates the T1 Framer Block has an interrupt request awaiting service. Interrupt service routine should branch to the interrupt source and read the T1 Framer status register (address 0xnB04) to clear the interrupt NOTE: This bit will be reset to 0 after the microprocessor has performed a read to the T1 Framer Interrupt Status register. TABLE 78: BLOCK INTERRUPT STATUS REGISTER (BISR) HEX ADDRESS: 0XnB00 BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION |
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