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XRT86VL34 bảng dữ liệu(PDF) 91 Page - Exar Corporation |
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XRT86VL34 bảng dữ liệu(HTML) 91 Page - Exar Corporation |
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91 / 156 page  XRT86VL34 86 REV. V1.2.0 QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION TABLE 73: TRANSMIT SLIP COUNTER (TSC) HEX ADDRESS: 0Xn90F BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION 7 TxSLIP[7] RUR 0 Performance Monitor - Transmit Slip Counter (8-bit Counter) These Reset-Upon-Read bit fields reflect the cumulative number of instances that Transmit Slip events have been detected by the T1 Framer since the last read of this register. NOTE: A slip event is defined as a replication or deletion of a T1 frame by the transmit slip buffer. 6 TxSLIP[6] RUR 0 5 TxSLIP[5] RUR 0 4 TxSLIP[4] RUR 0 3 TxSLIP[3] RUR 0 2 TxSLIP[2] RUR 0 1 TxSLIP[1] RUR 0 0 TxSLIP[0] RUR 0 TABLE 74: EXCESSIVE ZERO VIOLATION COUNTER MSB (EZVCU) HEX ADDRESS: 0Xn910 BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION 7 EZVC[15] RUR 0 Performance Monitor - T1 Excessive Zero Violation 16-Bit Counter - Upper Byte: These RESET-upon-READ bits, along with that within the “PMON T1 Excessive Zero Violation Counter Register LSB” combine to reflect the cumulative number of instances that the ReceiveT1 Excessive Zero Violation has been detected by the Receive T1 Framer block since the last read of this register. This register contains the Most Significant byte of this 16-bit of the Receive T1 Excessive Zero Violation counter. NOTE: For all 16-bit wide PMON registers, user must read the MSB counter first before reading the LSB counter in order to read the accurate PMON counts. To clear PMON count, user must read the MSB counter first before reading the LSB counter in order to clear the PMON count. 6 EZVC[14] RUR 0 5 EZVC[13] RUR 0 4 EZVC[12] RUR 0 3 EZVC[11] RUR 0 2 EZVC[10] RUR 0 1 EZVC[9] RUR 0 0 EZVC[8] RUR 0 TABLE 75: EXCESSIVE ZERO VIOLATION COUNTER LSB (EZVCL) HEX ADDRESS: 0Xn911 BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION 7 EZVC[7] RUR 0 Performance Monitor - T1 Excessive Zero Violation 16-Bit Counter - Lower Byte: These RESET-upon-READ bits, along with that within the “PMON T1 Excessive Zero Violation Counter Register MSB” combine to reflect the cumulative number of instances that the ReceiveT1 Excessive Zero Violation has been detected by the Receive T1 Framer block since the last read of this register. This register contains the Least Significant byte of this 16-bit of the Receive T1 Excessive Zero Violation counter. NOTE: For all 16-bit wide PMON registers, user must read the MSB counter first before reading the LSB counter in order to read the accurate PMON counts. To clear PMON count, user must read the MSB counter first before reading the LSB counter in order to clear the PMON count. 6 EZVC[6] RUR 0 5 EZVC[5] RUR 0 4 EZVC[4] RUR 0 3 EZVC[3] RUR 0 2 EZVC[2] RUR 0 1 EZVC[1] RUR 0 0 EZVC[0] RUR 0 |
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