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XRT86VL34 bảng dữ liệu(PDF) 49 Page - Exar Corporation

tên linh kiện XRT86VL34
Giải thích chi tiết về linh kiện  QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
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nhà sản xuất  EXAR [Exar Corporation]
Trang chủ  http://www.exar.com
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XRT86VL34 bảng dữ liệu(HTML) 49 Page - Exar Corporation

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XRT86VL34
44
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
1-0
TxIMODE[1:0]
R/W
00
Transmit Interface Mode selection
This bit determines the transmit interface speed. The exact function of these
two bits depends on whether Multiplexed mode is enabled or disabled.
Table 29 and Table 30 shows the functions of these two bits for non-multi-
plexed and multiplexed modes.:
TABLE 28: TRANSMIT INTERFACE CONTROL REGISTER (TICR)
HEX ADDRESS:0Xn120
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
TABLE 29: TRANSMIT INTERFACE SPEED WHEN MULTIPLEXED MODE IS
DISABLED (TXMUXEN = 0)
TXIMODE[1:0]
TRANSMIT INTERFACE SPEED
00
1.544Mbit/s Base Rate Mode:
Transmit Backplane interface signals include:
TxSERCLK is an input or output clock at 1.544MHz
TxMSYNC is the superframe boundary at 3ms (ESF) or
1.5ms (SF)
TxSYNC is the single frame boundary at 125 us
TxSER is the base-rate data input
01
2.048Mbit/s (High-Speed MVIP Mode):
Transmit backplane interface signals include:
TxSERCLK is an input clock at 1.544MHz
TxMSYNC is the high speed input clock at 2.048MHz to
input high-speed data
TxSYNC can be configured as a single frame or super-
frame boundary, depending on the setting of bit 5 of reg-
ister 0xn109
TxSER is the high-speed data input
10
4.096Mbit/s High-Speed Mode:
Transmit Backplane interface signals include:
TxSERCLK is an input clock at 1.544MHz
TxMSYNC will become the high speed input clock at
4.096MHz to input high-speed data
TxSYNC can be configured as a single frame or super-
frame boundary, depending on the setting of bit 5 of reg-
ister 0xn109
TxSER is the high-speed data input
11
8.192Mbit/s High-Speed Mode:
Transmit Backplane interface signals include:
TxSERCLK is an input clock at 1.544MHz
TxMSYNC will become the high speed input clock at
8.192MHz to input high-speed data
TxSYNC can be configured as a single frame or super-
frame boundary, depending on the setting of bit 5 of reg-
ister 0xn109
TxSER is the high-speed data input



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