MPC8555CPXAPF datasheet(17/88 Pages) FREESCALE

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MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

DDR SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the

MPC8555E.

6.1

DDR SDRAM DC Electrical Characteristics

Table 11 provides the recommended operating conditions for the DDR SDRAM component(s) of the

MPC8555E.

Table 12 provides the DDR capacitance.

Table 11. DDR SDRAM DC Electrical Characteristics

Parameter/Condition

Symbol

Min

Max

Unit

Notes

I/O supply voltage

GVDD

2.375

2.625

I/O reference voltage

MVREF

0.49

× GV

0.51

× GV

I/O termination voltage

VTT

MVREF – 0.04

MVREF + 0.04

Input high voltage

VIH

MVREF + 0.18

GVDD + 0.3

Input low voltage

VIL

–0.3

MVREF – 0.18

Output leakage current

IOZ

–10

μA4

Output high current (VOUT = 1.95 V)

IOH

–15.2

—

Output low current (VOUT = 0.35 V)

IOL

15.2

—

MVREF input leakage current

IVREF

—5

μA

Notes:

1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.

2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of MVREF.

4. Output leakage is measured with all outputs disabled, 0 V

≤ V

OUT ≤ GVDD.

Table 12. DDR SDRAM Capacitance

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS, MSYNC_IN

CIO

Delta input/output capacitance: DQ, DQS

CDIO

—0.5

Note:

1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak to peak) = 0.2 V.

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