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MPC8555CPXAPF bảng dữ liệu(PDF) 66 Page - Freescale Semiconductor, Inc

tên linh kiện MPC8555CPXAPF
Giải thích chi tiết về linh kiện  PowerQUICC??III Integrated Communications Processor Hardware Specifications
PDF  88 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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MPC8555CPXAPF bảng dữ liệu(HTML) 66 Page - Freescale Semiconductor, Inc

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MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
66
Freescale Semiconductor
Clocking
15.2
Platform/System PLL Ratio
The platform clock is the clock that drives the L2 cache, the DDR SDRAM data rate, and the e500 core
complex bus (CCB), and is also called the CCB clock. The values are determined by the binary value on
LA[28:31] at power up, as shown in Table 46.
There is no default for this PLL ratio; these signals must be pulled to the desired values.
For specifications on the PCI_CLK, refer to the PCI 2.2 Specification.
Table 46. CCB Clock Ratio
Binary Value of
LA[28:31] Signals
Ratio Description
0000
16:1 ratio CCB clock: SYSCLK (PCI bus)
0001
Reserved
0010
2:1 ratio CCB clock: SYSCLK (PCI bus)
0011
3:1 ratio CCB clock: SYSCLK (PCI bus)
0100
4:1 ratio CCB clock: SYSCLK (PCI bus)
0101
5:1 ratio CCB clock: SYSCLK (PCI bus)
0110
6:1 ratio CCB clock: SYSCLK (PCI bus)
0111
Reserved
1000
8:1 ratio CCB clock: SYSCLK (PCI bus)
1001
9:1 ratio CCB clock: SYSCLK (PCI bus)
1010
10:1 ratio CCB clock: SYSCLK (PCI bus)
1011
Reserved
1100
12:1 ratio CCB clock: SYSCLK (PCI bus)
1101
Reserved
1110
Reserved
1111
Reserved



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