MPC8540CVT667JC datasheet(63/104 Pages) FREESCALE

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MPC8540 Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

RapidIO

The compliance of receiver input signals RD[0:15] and RFRAME with their minimum data valid window

(DV) specification shall be determined by generating an eye pattern for each of the data signals and

comparing the eye pattern of each data signal with the RapidIO receive mask shown in Figure 39. The

value of X2 used to construct the mask shall be (1 – DVmin)/2. The ±100 mV minimum data valid and

±600 mV maximum input voltage values are from the DC specification. A signal is compliant with the data

valid window specification if and only if the receive mask can be positioned on the signal’s eye pattern

such that the eye pattern falls entirely within the unshaded portion of the mask.

Figure 39. RapidIO Receive Mask

The eye pattern for a data signal is generated by making a large number of recordings of the signal and

then overlaying the recordings. The number of recordings used to generate the eye shall be large enough

that further increasing the number of recordings used does not cause the resulting eye pattern to change

from one that complies with the RapidIO receive mask to one that does not. Each data signal in the

interface shall be carrying random or pseudo-random data when the recordings are made. If

pseudo-random data is used, the length of the pseudo-random sequence (repeat length) shall be long

Table 52. RapidIO Receiver AC Timing Specifications—1 Gbps Data Rate

Characteristic

Symbol

Range

Unit

Notes

Min

Max

Duty cycle of the clock input

1, 5

Data valid

425

—

Allowable static skew between any two data inputs

within a 8-/9-bit group

tDPAIR

—

300

Allowable static skew of data inputs to associated clock

tSKEW,PAIR

–200

200

Notes:

1.Measured at VID = 0 V.

2.Measured using the RapidIO receive mask shown in Figure 39.

3.See Figure 42.

4.See Figure 41 and Figure 42.

5.Guaranteed by design.

600

100

–100

–600

1–X2

Time (UI)

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