MPC8540CVT667JC datasheet(35/104 Pages) FREESCALE

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MPC8540 Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Ethernet: Three-Speed,10/100, MII Management

8.4.2 MII Management AC Electrical Specifications

Table 34 provides the MII management AC timing specifications.

Figure 16 shows the MII management AC timing diagram.

Figure 16. MII Management Interface Timing Diagram

Table 34. MII Management AC Timing Specifications

At recommended operating conditions with OVDD is 3.3 V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

Notes

MDC frequency

fMDC

0.893

—

10.4

MHz

2, 4

MDC period

tMDC

—

1120

MDC clock pulse width high

tMDCH

—

MDC to MDIO valid

tMDKHDV

2*[1/(fccb_clk/8)]

MDC to MDIO delay

tMDKHDX

—

2*[1/(fccb_clk/8)]

MDIO to MDC setup time

tMDDVKH

5—

—

MDIO to MDC hold time

tMDDXKH

0—

—

MDC rise time

tMDCR

—

MDC fall time

tMDHF

—

Notes:

1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX

symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are

invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data

input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup

time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2.This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the maximum frequency is

8.3 MHz and the minimum frequency is 1.2 MHz; for a CCB clock of 333 MHz, the maximum frequency is 10.4 MHz

and the minimum frequency is 1.5 MHz).

3.This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the delay is 60 ns and for a

CCB clock of 333 MHz, the delay is 48 ns).

4.Guaranteed by design.

MDC

tMDDXKH

tMDC

tMDCH

tMDCR

tMDCF

tMDDVKH

tMDKHDX

MDIO

(Input)

(Output)

tMDKHDV

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