MPC8540CVT667JC datasheet(38/104 Pages) FREESCALE

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MPC8540 Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Local Bus

Table 37 describes the general timing parameters of the local bus interface of the MPC8540 with the DLL

bypassed.

Table 37. Local Bus General Timing Parameters—DLL Bypassed

Parameter

POR Configuration

Symbol 1

Min

Max

Unit

Notes

Local bus cycle time

tLBK

6.0

—

Internal launch/capture clock to LCLK

delay

tLBKHKT

2.3

3.9

LCLK[n] skew to LCLK[m] or LSYNC_OUT

tLBKSKEW

—

150

3, 9

Input setup to local bus clock (except

LUPWAIT)

tLBIVKH1

5.7

—

4, 5

LUPWAIT input setup to local bus clock

tLBIVKH2

5.6

—

4, 5

Input hold from local bus clock (except

LUPWAIT)

tLBIXKH1

-1.8

—

4, 5

LUPWAIT input hold from local bus clock

tLBIXKH2

-1.3

—

4, 5

LALE output transition to LAD/LDP output

transition (LATCH hold time)

tLBOTOT

1.5

—

Local bus clock to output valid (except

LAD/LDP and LALE)

TSEC2_TXD[6:5] = 00

tLBKLOV1

—-0.3

TSEC2_TXD[6:5] = 11

(default)

1.2

Local bus clock to data valid for LAD/LDP

TSEC2_TXD[6:5] = 00

tLBKLOV2

—-0.1

TSEC2_TXD[6:5] = 11

(default)

1.4

Local bus clock to address valid for LAD

TSEC2_TXD[6:5] = 00

tLBKLOV3

—0

TSEC2_TXD[6:5] = 11

(default)

1.5

Local bus clock to LALE assertion

tLBKHOV4

—0

Output hold from local bus clock (except

LAD/LDP and LALE)

TSEC2_TXD[6:5] = 00

tLBKLOX1

-3.2

—

TSEC2_TXD[6:5] = 11

(default)

-2.3

Output hold from local bus clock for

LAD/LDP

TSEC2_TXD[6:5] = 00

tLBKLOX2

-3.2

—

TSEC2_TXD[6:5] = 11

(default)

-2.3

Local bus clock to output high Impedance

(except LAD/LDP and LALE)

TSEC2_TXD[6:5] = 00

tLBKLOZ1

—0.2

TSEC2_TXD[6:5] = 11

(default)

1.5

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