+

±

10M

470 k

470 k

0.01 F

Output

R1

R2

R3

C1

U1

VREF

VIN

Figure 6-18. Pulse Slicer

For this design, follow these design requirements:

• The RC constant value (R2 and C1) must support the targeted data rate to maintain a valid tripping threshold.

• The hysteresis introduced with R2 and R43 helps to avoid spurious output toggles.

The TLV1822-EP may also be used, but with the addition of a pull-up resistor on the output (not shown for

clarity).

Figure 6-19 shows the results of a 9600 baud data signal riding on a varying baseline.

V

OUT

V

IN

V

REF

1.8 V

1.2 V

4.0 V

0.0 V

1.61 V

1.58 V

Time

0.0

200.0 u

400.0 u

600.0 u

800.0 u

Figure 6-19. Pulse Slicer Waveforms

6.3 Power Supply Recommendations

Due to the fast output edges, it is critical to have bypass capacitors on the supply pin to prevent supply ringing

and false triggers and oscillations. Bypass the supply directly at each device with a low ESR 0.1µF ceramic

bypass capacitor directly between VCC pin and ground pins. Narrow, peak currents will be drawn during the

output transition time, particularly for the push-pull output device. These narrow pulses can cause un-bypassed

supply lines and poor grounds to ring, possibly causing variation that can eat into the input voltage range and

create an inaccurate comparison or even oscillations.

The device may be powered from both "split" supplies (V+ and V-), or "single" supplies (V+ and GND), with GND

applied to the V- pin. Input signals must stay within the specified input range (between V+ and V-) for either type.

Note that with a "split" supply the ouptut will now swing "low" (VOL) to V- potential and not GND.

TLV1812-EP, TLV1822-EP

SNOSDJ3 – MAY 2024

www.ti.com

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