6.1.1.3 Overdrive Voltage

The overdrive voltage, VOD, is the amount of input voltage beyond the reference voltage (and not the total input

peak-to-peak voltage). The overdrive voltage is 100mV as shown in the Figure 6-1 example. The overdrive

voltage can influence the propagation delay (tp). The smaller the overdrive voltage, the longer the propagation

delay, particularly when <100mV. If the fastest speeds are desired, it is recommended to apply the highest

amount of overdrive possible.

The risetime (tr) and falltime (tf) is the time from the 20% and 80% points of the output waveform.

6.1.2 Hysteresis

The basic comparator configuration may oscillate or produce a noisy "chatter" output if the applied differential

input voltage is near the comparator's offset voltage. This usually occurs when the input signal is moving very

slowly across the switching threshold of the comparator.

This problem can be prevented by the addition of hysteresis or positive feedback.

The hysteresis transfer curve is shown in Figure 6-2. This curve is a function of three components: VTH, VOS,

and VHYST:

• VTH is the actual set voltage or threshold trip voltage.

• VOS is the internal offset voltage between VIN+ and VIN–. This voltage is added to VTH to form the actual trip

point at which the comparator must respond to change output states.

• VHYST is the hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise.

VTH + VOS ± (VHYST / 2)

VTH + VOS + (VHYST / 2)

VTH + VOS

Figure 6-2. Hysteresis Transfer Curve

For more information, see the Comparator with and without hysteresis circuit application note.

6.1.2.1 Inverting Comparator With Hysteresis

The inverting comparator with hysteresis requires a three-resistor network that is referenced to the comparator

supply voltage (VCC), as shown in Figure 6-3.

R1

1 0Ÿ

+VCC

+5 V

VIN

R3

1 0Ÿ

+

±

R2

1 0Ÿ

VO

VA

5 V

0 V

VA2

VA1

VO

1.67 V

3.33 V

VIN

Figure 6-3. TLV1812-EPin an Inverting Configuration With Hysteresis

The equivalent resistor networks when the output is high and low are shown in Figure 6-3.

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