LR4102 datasheet(15/32 Pages) LSI

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TinyRISC LR4102 Microprocessor

FBus Interface

CBEN[3:0]

Command/byte enable

Bidirectional

DEVSELN

Device select

Bidirectional

FADDRP[28:0]

Demultiplexed address bus

Output

FADP[31:0]

Multiplexed address/Data bus

Bidirectional

FALEP

Address latch enable

Output

FRAMEN

Cycle frame indicating a bus transaction is

beginning

Bidirectional

GNTN

Grant the FBus

Output

GP[5:0]

General-purpose pins

Bidirectional

GPIO[3:0]

General-purpose I/O pins

Bidirectional

GPRDN

General-purpose read enable

Output

GPWEN[3:0]

General-purpose write byte enable

Output

IRDYN

Initiator ready

Bidirectional

REQN

Request FBus

Input

SD_CASN0_DMP0

DRAM CAS0 or SDRAM data mask 0

Output

SD_CASN1_DMP1

DRAM CAS1 or SDRAM data mask 1

Output

SD_CASN2_DMP2

DRAM CAS2 or SDRAM data mask 2

Output

SD_CASN3_DMP3

DRAM CAS3 or SDRAM data mask 3

Output

SD_OEN_CASN

DRAM output enable or SDRAM CAS

Output

SDONEP

Snooping done

Output

SD_RASN

SDRAM RAS

Output

SD_RASN0_CSN0

DRAM RAS bank 0 or SDRAM CAS0

Output

SD_RASN1_CSN1

DRAM RAS bank 1 or SDRAM CAS1

Output

SD_WEN_WEN

DRAM write enable or SDRAM write enable Output

STOPN

Stop transaction

Bidirectional

Table 5

LR4102 Signal List (Cont.)

Signal Group

Mnemonic Name

Functional Description

I/O

(Sheet 3 of 4)

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