LR4102 datasheet(14/32 Pages) LSI

14 / 32 page

TinyRISC LR4102 Microprocessor

Clocking

Interface

EXTAL

Input from crystal/Oscillator

Input

XTAL

Output to crystal

Output

PBCLKP

FAPI clock

Output

SDCLKP

SDRAM clock

Output

DIVC[1:0]

The divide value for DIV C upon reset

Input

DIVA[1:0]

The divide value for DIV A

Input

SELECT_PLLN

Control clock source MUX

Input

RESET_OUTN

Delayed reset signal for FAPI bus

Output

PLLENP

Enable PLL

Input

PLLENARSTP

Enable PLL auto reset

Input

Timer Interface

T0_OUTN

Timer 0 output

Output

T1_OUTN

Timer 1 output

Output

SerialICE-1

Interface

ICECLKP

SerialICE-1 Port clock

Input

ICERXP

SerialICE-1 Port receive

Input

ICETXP

SerialICE-1 Port transmit

Output

EJTAG Interface

and JTAG

boundary scan

signals

TCK

EJTAG Interface clock

Input

TMS

EJTAG Interface mode select

Input

TDI_DINT

EJTAG Interface data in/Debug interrupt

Input

TDO_TPC

EJTAG Interface data out/PC out

Output

TRST

EJTAG Interface reset

Input

PC Trace Output DCLK

PC Trace clock output

Output

PCST1[2:0]

PC Trace status set 1 [2:0]

Output

TPC[4:2]

PC Trace PC out [4:2]

Output

Table 5

LR4102 Signal List (Cont.)

Signal Group

Mnemonic Name

Functional Description

I/O

(Sheet 2 of 4)

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