IA186EM-PQF100I-R datasheet(11/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

F2 F1 F0

Divider Factor

Divide by 1 (20)

Divide by 2 (21)

Divide by 4 (22)

Divide by 8 (23)

Divide by 16 (24)

Divide by 32 (25)

Divide by 64 (26)

Divide by 128 (27)

EDRAM (0e4h) - The Enable RCU Register provides control and status for the refresh counter.

The EDRAM register contains 0000h at reset.

7 6 5 4 3 2

T [8:0]

E (bit 15) – When set to 1, the refresh counter is enabled and msc3_n is configured to act as rfsh_n.

Clearing E clears the refresh counter and disables refresh requests. The refresh address is unaffected

by clearing E.

RES (bits 14-9) – Reserved. These bits read back as 0.

T [8:0] (bits 8-0) – These bits hold the current value of the refresh counter. These bits are read-only.

CDRAM (0e2h) - The Clock Prescaler Register determines the period between refresh cycles.

The CDRAM register is undefined at reset.

7 6 5 4 3 2

RC [8:0]

RES (bits 15-9) – Reserved. These bits read back as 0.

RC [8:0] (bits 8-0) – These bits hold the clock count interval between refresh cycles. This value

should not be set to less than 18 (12h), else there would never be sufficient bus cycles available for the

processor to execute code.

In power-save mode, the refresh counter value should be adjusted to account for the clock divider

value in SYSCON.

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