IA186EM-PQF100I-R datasheet(42/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

PRM2 – PRM0

Reserved (bits 15 – 3) – Set to 0.

PRM 2-PRM0 (bits 2 - 0) Priority Field Mask. This three-bit field sets the minimum priority

necessary for a maskable interrupt to generate an interrupt. Any maskable interrupt with a

numerically higher value than that contained by these three bits is masked.

Priority Level

Priority

PR2 – PR0

(High) 0

0 0 0b

0 0 1b

0 1 0b

0 1 1b

1 0 0b

1 0 1b

1 1 0b

(Low) 7

1 1 1b

Any unmasked interrupt can generate an interrupt if the priority level is set to 7. On the other hand, if

the priority level is set to say 4, only unmasked interrupts with a priority of 0 to 5 are permitted to

generate interrupts.

IMASK (028h) – Interrupt MASK Register.

Master Mode

The interrupt mask register is read/write. Setting a bit in this register is effectively the same as setting the

MSK bit in the corresponding interrupt control register. Setting a bit to 1 masks the interrupt. The

interrupt request is enabled when the corresponding bit is set to 0.

The IMASK register contains 07fdh on reset

Reserved

SPI WD I4 I3 I2 I1 I0

D1-D0

Res

TMR

Reserved (bits 15 – 11)

SPI (bit 10) – Serial Port Interrupt Mask. Setting this bit to 1 is an indication that the asynchronous

serial port interrupt is masked.

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