IA186EM-PQF100I-R datasheet(33/133 Pages) INNOVASIC

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IA186EM/IA188EM

Data Sheet

8/16-BIT Microcontrollers

As of Production Version -03

TC [15:0] (bits 15-0) – Timer Count Value. This register has the value of the current count of the

related timer that is incremented every fourth processor clock in internal clocked mode. Alternatively,

the register is incremented each time the Timer 2 maxcount is reached if using Timer 2 as a prescaler.

Timer 0 and Timer 1 may be externally clocked by tmrin0 and tmrin1 signals.

SPICON (044h) - Serial Port Interrupt CONtrol Register.

Master Mode

This register controls the operation of the asynchronous serial port interrupt source (SPI, bit 10 in of the

Interrupt Request register)

The value of this register is 001Fh at reset.

Reserved

Res

MSK

PR2-PR0

Reserved (bits 15-5) – Set to 0.

Reserved (bit 4) – Set to1.

MSK (bit 3) – Mask. This bit, when 0, enables the serial port to cause an interrupt. When this bit is 1,

the serial port is prevented from generating an interrupt.

PR2-PR0 (bits 2-0) – Priority. These bits define the priority of the serial port interrupt in relation to

other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2 – PR0 are

shown in the following table.

Priority Level

Priority

PR2 – PR0

(High) 0

000b

001b

010b

011b

100b

101b

110b

(Low) 7

111b

WDCON (044h) – WatchDog timer interrupt CONtrol Register.

Master Mode

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