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TLV9151 bảng dữ liệu(PDF) 10 Page - Texas Instruments |
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TLV9151 bảng dữ liệu(HTML) 10 Page - Texas Instruments |
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10 / 60 page ![]() 5.7 Electrical Characteristics (continued) For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VO UT = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SHDN pin input bias current (per pin) VS = 2.7 V to 16 V, (V+) ≥ SHDN ≥ (V–) + 0.9 V 500 nA VS = 2.7 V to 16 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V 150 (1) Third-order filter; bandwidth = 80 kHz at –3 dB. (2) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level. (3) Full shutdown refers to the dual TLVxx2S having both channels 1 and 2 disabled (SHDN1 = SHDN2 = V–) and the quad TLV9xx4S having all channels 1 to 4 disabled (SHDN12 = SHDN34 = V–). For partial shutdown, only one SHDN pin is exercised; in this mode, the internal biasing circuitry remains operational and the enable time is shorter. (4) Specified by characterization only. TLV9151-Q1, TLV9152-Q1, TLV9154-Q1 SBOSA23G – MAY 2020 – REVISED MARCH 2024 www.ti.com 10 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TLV9151-Q1 TLV9152-Q1 TLV9154-Q1 |
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