TLV9151 datasheet(21/60 Pages) TI1

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For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small

resistor, RISO, in series with the output, as shown in Figure 6-5. This resistor significantly reduces ringing

and maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the

capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing

the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low

output levels. The high capacitive load drive of the TLV915x-Q1 is designed for applications such as reference

buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 6-5 uses an isolation resistor,

RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase

margin.

load

out

iso

-V

Figure 6-5. Extending Capacitive Load Drive With the TLV9151-Q1

6.3.4 Common-Mode Voltage Range

The TLV915x-Q1 is a 16-V, rail-to-rail input operational amplifier with an input common-mode range that extends

200 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel and

P-channel differential input pairs, as shown in Figure 6-6. The N-channel pair is active for input voltages close to

the positive rail, typically (V+) – 1 V to 100 mV above the positive supply. The P-channel pair is active for inputs

from 100 mV below the negative supply to approximately (V+) – 2 V. There is a small transition region, typically

(V+) – 2 V to (V+) – 1 V in which both input pairs are on. This transition region can vary modestly with process

variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance may be

degraded compared to operation outside this region.

Figure 5-5 shows this transition region for a typical device in terms of input voltage offset in more detail.

For more information on common-mode voltage range and PMOS/NMOS pair interaction, see Op Amps With

Complementary-Pair Input Stages application note.

NMOS

PMOS

NMOS

V-

V+

IN+

IN-

Figure 6-6. Rail-to-Rail Input Stage

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TLV9151-Q1, TLV9152-Q1, TLV9154-Q1

SBOSA23G – MAY 2020 – REVISED MARCH 2024

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