TLV9151 datasheet(8/60 Pages) TI1

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5.7 Electrical Characteristics

For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and

VO UT = VS / 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

VOS

Input offset voltage

VCM = V–

±125

±895

µV

TA = –40°C to 125°C

±925

dVOS/dT

Input offset voltage drift

TA = –40°C to 125°C

±0.3

µV/

℃

PSRR

Input offset voltage

versus power supply

VCM = V–, VS = 4 V to 16 V

TA = –40°C to 125°C

±0.3

±1.5

μV/V

VCM = V–, VS = 2.7 V to 16 V(4)

±1

±10.6

Channel separation

f = 0 Hz

µV/V

INPUT BIAS CURRENT

Input bias current

±10

TA = –40°C to 125°C(4)

±1

IOS

Input offset current

±10

TA = –40°C to 125°C(4)

±1

NOISE

Input voltage noise

f = 0.1 Hz to 10 Hz

1.8

μVPP

0.3

µVRMS

Input voltage noise

density

f = 1 kHz

10.8

nV/√Hz

f = 10 kHz

9.4

Input current noise

f = 1 kHz

fA/√Hz

INPUT VOLTAGE RANGE

VCM

Common-mode voltage

range

(V–) – 0.1

(V+) + 0.1

CMRR

Common-mode rejection

ratio

VS = 16 V, (V–) – 0.1 V < VCM < (V+)

– 2 V (Main input pair)

TA = –40°C to 125°C

130

VS = 4 V, (V–) – 0.1 V < VCM < (V+) –

2 V (Main input pair)

100

VS = 2.7 V, (V–) – 0.1 V < VCM < (V+)

– 2 V (Main input pair)(4)

VS = 2.7 V to 16 V, (V+) – 1 V < VCM

< (V+) + 0.1 V (Aux input pair)

INPUT CAPACITANCE

ZID

Differential

100 || 9

MΩ || pF

ZICM

Common-mode

6 || 1

TΩ || pF

OPEN-LOOP GAIN

AOL

Open-loop voltage gain

VS = 16 V, VCM = V–

(V–) + 0.1 V < VO < (V+) – 0.1 V

120

145

TA = –40°C to 125°C

142

VS = 4 V, VCM = V–

(V–) + 0.1 V < VO < (V+) – 0.1 V

104

130

TA = –40°C to 125°C

125

VS = 2.7 V, VCM = V–

(V–) + 0.1 V < VO < (V+) – 0.1 V(4)

101

120

TA = –40°C to 125°C

118

TLV9151-Q1, TLV9152-Q1, TLV9154-Q1

SBOSA23G – MAY 2020 – REVISED MARCH 2024

www.ti.com

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