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ADMFM2000ABVZ bảng dữ liệu(PDF) 22 Page - Analog Devices

tên linh kiện ADMFM2000ABVZ
Giải thích chi tiết về linh kiện  Dual-Channel, 0.5 GHz to 32 GHz, Microwave Downconverter
PDF  28 Pages
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nhà sản xuất  AD [Analog Devices]
Trang chủ  http://www.analog.com
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Data Sheet
ADMFM2000
THEORY OF OPERATION
analog.com
Rev. 0 | 22 of 28
LPF
A LPF with a bandwidth of 8 GHz after the switch rejects har-
monics and other spurs generated from the mixer or induced on
the RF_BYPASS_IN_1 and RF_BYPASS_IN_2 input pins when in
direct IF mode of operation.
DSA
The DSA after the LPF provides a 31 dB of gain control range with
1 dB step size. The DSA attenuation is set by the logic levels on
the DSAx_V0 to DSAx_V4 pins (see Figure 3 and Table 8). All pins
at high sets the minimum attenuation level and all pins at low sets
the maximum attenuation. Note that the DSA requires a negative
supply of −5 V on the VSS_DSAS pin, and that the logic controls on
these pins are positive (0 V and 5 V).
Table 8. DSA Attenuation Truth Table for DSA1_V0, DSA1_V1, DSA1_V2, DSA1_V3, and DSA1_V4 and DSA2_V0, DSA2_V1, DSA2_V2, DSA2_V3, and DSA2_V4
Digital Control Input1
Attenuation State (dB)
DSAx_V4
DSAx_V3
DSAx_V2
DSAx_V1
DSAx_V0
High
High
High
High
High
0 (reference)
High
High
High
High
Low
1
High
High
High
Low
High
2
High
High
High
Low
Low
3
High
High
Low
High
High
4
High
High
Low
High
Low
5
High
High
Low
Low
High
6
High
High
Low
Low
Low
7
High
Low
High
High
High
8
High
Low
High
High
Low
9
High
Low
High
Low
High
10
High
Low
High
Low
Low
11
High
Low
Low
High
High
12
High
Low
Low
High
Low
13
High
Low
Low
Low
High
14
High
Low
High
Low
Low
15
Low
High
High
High
High
16
Low
High
High
High
Low
17
Low
High
High
Low
High
18
Low
High
High
Low
Low
19
Low
High
Low
High
High
20
Low
High
Low
High
Low
21
Low
High
Low
Low
High
22
Low
High
Low
Low
Low
23
Low
Low
High
High
High
24
Low
Low
High
High
Low
25
Low
Low
High
Low
High
26
Low
Low
High
Low
Low
27
Low
Low
Low
High
High
28
Low
Low
Low
High
Low
29
Low
Low
Low
Low
High
30
Low
Low
Low
Low
Low
31
1 Refer to the logic input in Table 1 for the logic level high and low detailed in Table 8.



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