AD4080BBCZ datasheet(24/95 Pages) AD

24 / 95 page

Data Sheet

AD4080

THEORY OF OPERATION

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Rev. 0 | 24 of 95

Figure 41. Power Supply Sequence, Externally Generated IOVDD, VDD11

POWER SAVING OPERATING MODES

The operating mode of AD4080 is controlled by the OPERAT-

ING_MODES bits in the Device Configuration Register (Address

0x02). On power up and after reset, the default is normal mode

(OPERATING_MODES = 00). Table 11 describes all operating

modes, and Figure 42 depicts the allowed transitions between

these modes. Note that direct transitions between the two power

saving modes (standby mode and sleep mode) are not permitted.

It is important to stop all conversion and data interface clocking

before configuring the power mode.

When in either standby mode or sleep mode, the VDD33 supply

can be removed to reduce power consumption. This supply must

be re-established prior to issuing the SPI configuration interface

command to exit either power saving mode.

Figure 42. Operating Mode Transitions

Transitioning from normal mode to either of the two power saving

modes is achieved by writing the required value to the OPERAT-

ING_MODES bits in the Device Configuration Register. Waking

up (that is, transitioning back to normal mode) is achieved in a

similar way because the SPI configuration interface operation is

not affected by any of the power saving modes (see the SPI Config-

uration Interface section). Standby mode can be selected to save

power, in the case where the user wants to quickly return to normal

conversions. Sleep mode is a lower power state where returning to

normal mode takes longer. Both standby and sleep mode can be

particularly useful when used with the result FIFO (see the Result

FIFO section), whereby previously stored conversion data can be

accessed from the FIFO while it is still in the selected power saving

mode.

To reduce power consumption in both standby and sleep mode,

the internal IOVDD LDO regulator is powered down. If the user

is not externally supplying IOVDD, all IOVDD domain inputs and

outputs are disabled (all GPIOx and all LVDS data interface (see

the LVDS Data Interface section) and SPI data interface (see the

SPI Data Interface section) signals are disabled). In this specific

condition, it is still possible to write to the AD4080 SPI configuration

to issue a command to return to normal mode by writing to the

OPERATING_MODES bits in the device configuration register (see

the Device Configuration Register section) or to issue a software

reset (see the Software Reset section). As GPIOx is disabled, it is

not possible to perform any read activity on the SPI configuration

interface bus.

When IOVDD is externally supplied, and the device is put into

standby or sleep mode, the LVDS data interface is disabled; howev-

er, all GPIOx, SPI data interface, and SPI configuration interface

pins remain enabled and unaffected. While power is supplied exter-

nally to IOVDD within its specified range, previously acquired data

stored in the result FIFO can be access in either standby or sleep

mode.

Table 11 also indicates the wake-up times associated with each of

the modes. Wake-up time from sleep mode is significantly higher

than that of standby mode because time must be allowed for

the internal reference and common-mode buffers to re-enable and

to replenish charge to the internal capacitors. When returning to

normal mode, the specified wake-up time must be satisfied before

applying the first conversion start pulse. This specified time is the

time it takes from when the SPI command to exit the selected

power saving mode is written to the device configuration register

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