AD4080BBCZ datasheet(54/95 Pages) AD

54 / 95 page

Data Sheet

AD4080

DIGITAL FEATURES

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Rev. 0 | 54 of 95

Event Detection Timing

When event detection is enabled in the general configuration regis-

ter (see the General Configuration Register section), the HI_DTCT

and LO_DTCT signals indicate the occurrence of an internally

generated event. These signals can be routed internally through the

following paths:

►

HI_DTCT and LO_DTCT are directly accessible via an enabled

GPIO with GPIO_x_SEL set to 0b100 or 0b101, respectively, a

threshold event can be monitored externally by a digital host via

the GPIO. Logic 1 on a configured GPIO indicates detection of

an event.

►

HI_DTCT and LO_DTCT can each be routed by setting the

HI_ROUTE and LO_ROUTE bits to 1, respectively, in the general

configuration register (Address 0x1C) to allow HI_DTCT and

LO_DTCT to propagate to the LO_STATUS and HI_STATUS bits

in the device status register (see the Device Status Register

section, Address 0x14). These status bits can be monitored by

the digital host via the configuration SPI. Logic 1 on a configured

GPIO indicates the detection of an event. Each of these two

bits are independently cleared when a 1 is written to these bits.

Power cycling or device reset also result in the bits clearing.

►

HI_DTCT and LO_DTCT can each be routed by setting the

HI_ROUTE and LO_ROUTE bits to 1, respectively, in the general

configuration register (Address 0x1C) to allow HI_DTCT and

LO_DTCT to propagate to the ALERT signal. Any enabled GPIO

set to output a status alert, that is, with GPIO_x_SEL set to

0b0110, routes the ALERT signal to the GPIO to indicate when

an event occurs. A GPIO configured in this mode is normally

high, with a logic low indicating that an event has occurred. As

indicated in the Figure 82 section, this GPIO remains low only

while the threshold level is crossed, and it returns to logic high as

soon as the threshold bound is no longer crossed, and the timing

in Figure 81 is satisfied.

Event detection is synchronous to the rising edge of the CNV+. A

latency of two conversion clock cycles exists from the first CNV+

edge where the analog input crosses a threshold to a detected

event that is flagged in the device status register and to any GPIO

configured to route ALERT. As is evident in Figure 80, where both

the HI_DTCT flag and ALERT routed to a GPIO are shown, the

behavior, once the threshold level is no longer crossed, is different.

When a CNV+ rising edge occurs where the analog input no

longer crosses the set threshold, ALERT de-asserts two conversion

cycles later, on the rising edge of CNV. Any HI_DTCT or LO_DTCT

already set is not cleared at this point. These signals are only

cleared by writing 1 to the relevant bits in the device status register

(Address 0x14) or where a device reset occurred.

Figure 81. Event Detection Timing

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