AD4080BBCZ datasheet(11/95 Pages) AD

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Data Sheet

AD4080

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 11 of 95

Table 6. Pin Function Descriptions (Continued)

Pin No.

Mnemonic

Type1

Description

falling edge of the data interface clock (DCLK). Note that this pin does not go into a

high impedance state when used in four-lane SPI mode when CS is inactive.

This pin must be left unconnected if not being used.

DA−/SDOB

Data Interface Output

In LVDS data interface mode (default), this output pin along with DA+ serves as the

primary LVDS Data Lane A. If unused, leave unconnected.

In SPI data interface mode, this pin functions as Serial Data Output B (SDOB). This is

the only active serial data output in single lane mode. Result data is shifted out of this

pin on the falling edge of the data interface clock (DCLK).

IN−

Negative Analog Differential Input.

AUXIN−

Negative Auxiliary Analog Differential Input.

GPIO1

DI/O

General-Purpose Input and Output 1 Pin.

SCLK

Configuration Interface Serial Data Clock. This clock input is used to shift data into and

out of the device configuration memory.

GPIO2

DI/O

General-Purpose Input and Output 2 Pin.

GPIO3

DI/O

General-Purpose Input and Output 3 Pin.

F3, G3

VDD33

3.3 V Supply Rail Inputs. These supply pins are internally decoupled by a 470 nF

capacitor to GND.

F4, G4

REFIN

3.0 V Reference Voltage Inputs.

SDI

Serial Data Input. Configuration data is shifted into this input on the rising edge of the

serial data clock, SCLK.

Configuration Interface Chip Select Input (Active Low). The CS input frames serial

data transfers over the configuration SPI.

CMO

Common-Mode Voltage (VCM) Output.

DNC

Do Not Connect.

GPIO0

DI/O

General-Purpose Input and Output 0 Pin.

1 AI is analog input, AO is analog output, DI is digital input; DI/O is digital input and output, DO is digital output, and P is power.

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