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AD4080BBCZ bảng dữ liệu(PDF) 45 Page - Analog Devices

tên linh kiện AD4080BBCZ
Giải thích chi tiết về linh kiện  20-Bit, 40 MSPS, Differential SAR ADC
PDF  95 Pages
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nhà sản xuất  AD [Analog Devices]
Trang chủ  http://www.analog.com
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AD4080BBCZ bảng dữ liệu(HTML) 45 Page - Analog Devices

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Data Sheet
AD4080
DIGITAL INTERFACE
analog.com
Rev. 0 | 45 of 95
Self Clock Mode
In LVDS data interface mode, it is possible to disable the DCO+
and DCO− echo clock output (see the Echo Clock Mode section)
by setting LVDS_SELF_CLK_MODE = 1 in the ADC Data Interface
Configuration B register (see the ADC Data Interface Configuration
B Register section, Address 0x16). This setting puts the device
in self clock mode disabling the DCO+ and DCO− output driver,
with the benefit of saving interface power as well as reducing the
number of LVDS pairs required to interface with the host controller.
In this mode, the DCO+ and DCO− pins can be left disconnected;
therefore, in single-lane configurations, a minimum of two LVDS
pairs (CLK+ and CLK−, DA+ and DA−) are required to connect to
each AD4080 instance. The interface connectivity can further be
simplified by sharing the interface clock (CLK+ and CLK−) between
multiple AD4080 instances.
Figure 74. Continuous Conversion Timing, LVDS Data Interface, Single Data Lane, Self Clock Mode
Figure 75. Continuous Conversion Timing, LVDS Data Interface, Dual Data Lane, Self Clock Mode



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