MPC8323ECVRADDC datasheet(14/80 Pages) FREESCALE

14 / 80 page

MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

DDR1 and DDR2 SDRAM

Table 13 provides the DDR2 capacitance when Dn_GVDD(typ) = 1.8 V.

Table 14 provides the recommended operating conditions for the DDR1 SDRAM component(s) of the

MPC8323E when Dn_GVDD(typ) = 2.5 V.

Table 15 provides the DDR1 capacitance Dn_GVDD(typ) = 2.5 V.

Table 13. DDR2 SDRAM Capacitance for D

_GVDD(typ) = 1.8 V

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS

CIO

Delta input/output capacitance: DQ, DQS

CDIO

—0.5

Note:

1. This parameter is sampled. D

_GV

DD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = Dn_GVDD/2,

VOUT (peak-to-peak) = 0.2 V.

Table 14. DDR1 SDRAM DC Electrical Characteristics for D

_GVDD(typ) = 2.5 V

Parameter/Condition

Symbol

Min

Max

Unit

Notes

I/O supply voltage

_GV

2.375

2.625

I/O reference voltage

MVREF

nREF

0.49

× Dn_GVDD

0.51

× Dn_GVDD

I/O termination voltage

VTT

MVREF

nREF – 0.04

MVREF

nREF + 0.04

Input high voltage

VIH

MVREF

nREF + 0.15

_GV

DD + 0.3

Input low voltage

VIL

–0.3

MVREF

nREF – 0.15

Output leakage current

IOZ

–9.9

μA4

Output high current (VOUT = 1.95 V)

IOH

–16.2

—

Output low current (VOUT = 0.35 V)

IOL

16.2

—

Notes:

1. D

_GV

DD is expected to be within 50 mV of the DRAM Dn_GVDD at all times.

2. MVREF

nREF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GVDD DC variations as measured at the receiver.

Peak-to-peak noise on MVREF

nREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF

nREF. This rail should track variations in the DC level of MVREFnREF.

4. Output leakage is measured with all outputs disabled, 0 V

≤ VOUT ≤ Dn_GVDD.

Table 15. DDR1 SDRAM Capacitance for D

_GVDD(typ) = 2.5 V Interface

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ,DQS

CIO

Delta input/output capacitance: DQ, DQS

CDIO

—0.5

Note:

1. This parameter is sampled. D

_GV

DD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = Dn_GVDD/2,

VOUT (peak-to-peak) = 0.2 V.

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