MPC8323ECVRADDC datasheet(77/80 Pages) FREESCALE

77 / 80 page

MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

Document Revision History

24.6

Configuration Pin Multiplexing

The MPC8323E provides the user with power-on configuration options which can be set through the use

of external pull-up or pull-down resistors of 4.7 k

Ω on certain output pins (see customer visible

configuration pins). These pins are generally used as output only pins in normal operation.

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins

while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled

and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these

pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize

the disruption of signal quality or speed for output pins thus configured.

24.7

Pull-Up Resistor Requirements

The MPC8323E requires high resistance pull-up resistors (10 k

Ω is recommended) on open drain type pins

including I2C pins, Ethernet Management MDIO pin, and IPIC interrupt pins.

For more information on required pull-up resistors and the connections required for the JTAG interface,

see AN3361, MPC8321E/MPC8323E PowerQUICC™ Design Checklist, Rev. 1.

25 Document Revision History

Table 66 provides a revision history for this hardware specification.

Table 66. Document Revision History

Rev.

No.

Date

Substantive Change(s)

06/2007

Initial release.

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