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MPC8323ECVRADDC bảng dữ liệu(PDF) 68 Page - Freescale Semiconductor, Inc

tên linh kiện MPC8323ECVRADDC
Giải thích chi tiết về linh kiện  PowerQUICC??II Pro Integrated Communications Processor Family Hardware Specifications
PDF  80 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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MPC8323ECVRADDC bảng dữ liệu(HTML) 68 Page - Freescale Semiconductor, Inc

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MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
68
Freescale Semiconductor
Clocking
22.6
QUICC Engine PLL Configuration
The QUICC Engine PLL is controlled by the RCWL[CEPMF] and RCWL[CEPDF] parameters. Table 61
shows the multiplication factor encodings for the QUICC Engine PLL.
The RCWL[CEVCOD] denotes the QUICC Engine PLL VCO internal frequency as shown in Table 62.
NOTE
The VCO divider (RCWL[CEVCOD]) must be set properly so that the
QUICC Engine VCO frequency is in the range of 300–600 MHz. The
QUICC Engine frequency is not restricted by the CSB and core frequencies.
The CSB, core, and QUICC Engine frequencies should be selected
according to the performance requirements.
The QUICC Engine VCO frequency is derived from the following
equations:
ce_clk = (primary clock input × CEPMF)
÷ (1 + CEPDF)
QUICC Engine VCO Frequency = ce_clk × VCO divider × (1 + CEPDF)
Table 61. QUICC Engine PLL Multiplication Factors
RCWL[CEPMF]
RCWL[CEPDF]
QUICC Engine PLL Multiplication
Factor = RCWL[CEPMF]/
(1 + RCWL[CEPDF)
00000–00001
0
Reserved
00010
0
× 2
00011
0
× 3
00100
0
× 4
00101
0
× 5
00110
0
× 6
00111
0
× 7
01000
0
× 8
01001–11111
0
Reserved
Table 62. QUICC Engine PLL VCO Divider
RCWL[CEVCOD]
VCO Divider
00
4
01
8
10
2
11
Reserved



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