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MPC8323ECVRADDC bảng dữ liệu(PDF) 67 Page - Freescale Semiconductor, Inc

tên linh kiện MPC8323ECVRADDC
Giải thích chi tiết về linh kiện  PowerQUICC??II Pro Integrated Communications Processor Family Hardware Specifications
PDF  80 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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MPC8323ECVRADDC bảng dữ liệu(HTML) 67 Page - Freescale Semiconductor, Inc

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MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Freescale Semiconductor
67
Clocking
22.5
Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 60 shows the encodings for RCWL[COREPLL]. COREPLL values not listed
in Table 60 should be considered reserved.
NOTE
Core VCO frequency = core frequency × VCO divider
VCO divider (RCWL[COREPLL[0:1]]) must be set properly so that the
core VCO frequency is in the range of 500–800 MHz.
Table 60. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk : csb_clk Ratio
VCO Divider
0-1
2-5
6
nn
0000
n
PLL bypassed
(PLL off,
csb_clk clocks
core directly)
PLL bypassed
(PLL off,
csb_clk clocks
core directly)
00
0001
01:1
÷2
01
0001
01:1
÷4
10
0001
01:1
÷8
11
0001
01:1
÷8
00
0001
11.5:1
÷2
01
0001
11.5:1
÷4
10
0001
11.5:1
÷8
11
0001
11.5:1
÷8
00
0010
02:1
÷2
01
0010
02:1
÷4
10
0010
02:1
÷8
11
0010
02:1
÷8
00
0010
12.5:1
÷2
01
0010
12.5:1
÷4
10
0010
12.5:1
÷8
11
0010
12.5:1
÷8
00
0011
03:1
÷2
01
0011
03:1
÷4
10
0011
03:1
÷8
11
0011
03:1
÷8



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