S32K310 datasheet(77/143 Pages) NXP

77 / 143 page

Table 34. Flash Read Wait State Settings (S32K358, S32K348, S32K338, S32K328 and S32K388) (continued)

Flash Frequency

RWSC setting

120 MHz < Freq ≤ 150 MHz

150 MHz < Freq ≤ 180 MHz

180 MHz < Freq ≤ 210 MHz

210 MHz < Freq ≤ 240 MHz

240 MHz < Freq ≤ 250 MHz

10 Analog modules

10.1 SAR_ADC

All below specs are applicable only when one ADC instance is in operation and averaging is used or multiple ADC instances are

operational at the same time but sampling different channels. Best performance can be achieved if only one ADC is operational

at a time sampling one channel

Table 35. SAR_ADC

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

VDD_HV_A

ADC Supply

Voltage 1

2.97

—

5.5

—

DVREFL

VSS / VREFL

Voltage Difference 2

-100

—

100

—

VAD_INPUT

ADC Input Voltage 3 VREFL

—

VREFH

—

fAD_CK

ADC Clock

Frequency

(S32K344,

S32K324, S32K314,

S32K342, S32K341,

S32K322)

—

MHz

—

fAD_CK

ADC Clock

Frequency

(S32K312,

S32K311, S32K310,

S32K358, S32K348,

S32K338, S32K328,

S32K388)

—

120

MHz

—

tSAMPLE

ADC Input Sampling

Time

275

—

tCONV

ADC Total

Conversion Time

—

12-bit result

—

Table continues on the next page...

NXP Semiconductors

Analog modules

S32K3xx Data Sheet, Rev. 9.1, 03/2024

Data Sheet: Technical Data

Preliminary Information for S32K388

77 / 143

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