S32K310 datasheet(76/143 Pages) NXP

76 / 143 page

Table 32. Flash memory AC timing specifications (continued)

Symbol

Characteristic

Min

Typical

Max

Units

taistart

Time from 0 to 1 transition of UT0[AIE] initiating a

Margin Read or Array Integrity until the UT0[AID]

bit is cleared. This time also applies to the

resuming from a suspend or breakpoint by

clearing UT0[AISUS] or clearing UT0[NAIBP]

—

taistop

Time from 1 to 0 transition of UT0[AIE] initiating

an Array Integrity abort until the UT0[AID] bit is

set. This time also applies to the UT0[AISUS] to

UT0[AID] setting in the event of a Array Integrity

suspend request.

—

system clock

periods

tmrstop

Time from 1 to 0 transition of UT0[AIE] initiating

a Margin Read abort until the UT0[AID] bit is

set. This time also applies to the UT0[AISUS] to

UT0[AID] setting in the event of a Margin Read

suspend request.

—

plus fifteen

system clock

periods

µs

1. For Block Erase, Tdones times may be 3x max spec.

2. In extreme cases (1 block configurations) Tdrcv min may be faster (12uS plus seven system clocks)

9.5 Flash memory read timing parameters

Table 33. Flash Read Wait State Settings (S32K344, S32K324, S32K314, S32K342, S32K322, S32K341, S32K312,

S32K311 and S32K310)

Flash Frequency

RWSC setting

250 KHz < Freq ≤ 66 MHz

66 MHz < Freq ≤ 100 MHz

100 MHz < Freq ≤ 133 MHz

133 MHz < Freq ≤ 167 MHz

167 MHz < Freq ≤ 200 MHz

200 MHz < Freq ≤ 233 MHz

233 MHz < Freq ≤ 250 MHz

Table 34. Flash Read Wait State Settings (S32K358, S32K348, S32K338, S32K328 and S32K388)

Flash Frequency

RWSC setting

250 KHz < Freq ≤ 60 MHz

60 MHz < Freq ≤ 90 MHz

90 MHz < Freq ≤ 120 MHz

Table continues on the next page...

NXP Semiconductors

Flash memory specification

S32K3xx Data Sheet, Rev. 9.1, 03/2024

Data Sheet: Technical Data

Preliminary Information for S32K388

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