PCD5096 datasheet(31/52 Pages) PHILIPS

31 / 52 page

1997 Jan 22

Philips Semiconductors

Preliminary speciﬁcation

Universal codec

PCD5096

Table 33 Pin redeﬁnition in Codec test loop mode

11.2

Codec test loop signal timing

The TEST_OUTPUT_x signal changes at the falling edge of CLK3, and the signal presented on TEST_INPUT_x is

sampled just before the falling edge of CLK3. Note that the 4fs serial PCM data shifted in via TEST_INPUT_x is only used

during the next FS4 HIGH period.

NORMAL MODE

CODEC TEST LOOP MODE

PIN NAME

SIGNAL NAME

I/O

DESCRIPTION

TEST_INPUT_1

108fs bitstream or 4fs serial data input to Codec 1

TEST_OUTPUT_1

108fs bitstream or 4fs serial data output from Codec 1

TEST_INPUT_2

108fs bitstream or 4fs serial data input to Codec 2

IO1

TEST_OUTPUT_2

108fs bitstream or 4fs serial data output from Codec 2

DCL

CLK3

3456 kHz bit clock signal (4

× 108fs) with 50% duty cycle

IO0

FS4

32 kHz word synchronization signal (4fs), duty cycle = 12/108

Fig.17 Codec test loop signal timing for 108fs 1-bit bitstream signals.

handbook, full pagewidth

MBH877

sample moment for 1 bit digital loop mode

sample moment for 1 bit analog loop mode

CLK3

FS4

FS1

TEST_OUTPUT_x

TEST_INPUT_x

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